explore Our
Publications
We research cyber security and teach future’s experts
to ensure secure technology in everyone’s life.
Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms
Hirner F., Streibl M., Krieger F., Mert A., Sinha Roy S.
ACM Conference on Computer and Communications Security (CCS) 2024, ACM/IEEE
Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs
Ravi P., Bhasin S., Chattopadhyay A., Aikata A., Sinha Roy S.
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024, 34th Great Lakes Symposium on VLSI, 216 - 221
Proteus: A Pipelined NTT Architecture Generator
Hirner F., Mert A., Sinha Roy S.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20(18)
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
Krieger F., Hirner F., Mert A., Sinha Roy S.
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024 Design, Automation and Test in Europe Conference
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
Krieger F., Hirner F., Mert A., Sinha Roy S.
2024 ACM/IEEE International Conference on Computer-Aided Design, ACM/IEEE
ModHE: Modular Homomorphic Encryption Using Module Lattices
Mukherjee A., Aikata A., Mert A., Lee Y., Kwon S., Deriyabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2024(1), 527-562
REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography
Pagliarini S., Aikata A., Imran M., Sinha Roy S.
AsiaCCS
Exploring the Advantages and Challenges of Fermat NTT in FHE Acceleration
Kim A., Mert A., Mukherjee A., Aikata A., Deryabin M., Kwon S., Kang H., Sinha Roy S.
44th Annual International Cryptology Conference - CRYPTO 2024, 44th Annual International Cryptology Conference
Secure and Efficient Outsourced Matrix Multiplication with Homomorphic Encryption
Aikata A., Sinha Roy S.
Indocrypt 2024, Indocrypt 2024
PASTA on Edge: Cryptoprocessor for Hybrid Homomorphic Encryption
Aikata A., Sanz Sobrino D., Sinha Roy S.
DATE: Design, Automation and Test in Europe Conference, 2024 Design, Automation and Test in Europe Conference
High-speed SABER Key Encapsulation Mechanism in 65nm CMOS
Imran M., Almeida F., Basso A., Sinha Roy S., Pagliarini S.
Journal of Cryptographic Engineering, Vol. 13(4), 461-471
Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography
Aikata A., Basso A., Cassiers G., Mert A., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2023(3), 366-390
A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Aikata A., Mert A., Jacquemin D., Das A., Matthews D., Ghosh S., Sinha Roy S.
IEEE Transactions on Computers, Vol. 72(6), 1568-1580
High-speed Design of Post Quantum Cryptography with Optimized Hashing and Multiplication
Imran M., Aikata A., Sinha Roy S., Pagliarini S.
IEEE Transactions on Circuits and Systems, Part II: Express Briefs , 1
Preventing a Cryptoapocalypse
Sinha Roy S., Banerjee U.
IEEE Solid-State Circuits Magazine, Vol. 15, 38-44
Medha: Microcoded Hardware Accelerator for computing on Encrypted Data
Mert A., Aikata A., Kwon S., Shiin Y., Yoo D., Lee Y., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2023(1), 463-500
Time-Memory Trade-Offs for Saber+ on Memory-Constrained RISC-V Platform
Zhang J., Huang J., Liu Z., Sinha Roy S.
IEEE Transactions on Computers, Vol. 71(11), 2996-3007
KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium
Aikata A., Mert A., Imran M., Pagliarini S., Sinha Roy S.
IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 2022, 1-12
Will You Cross the Threshold for Me? Generic Side-Channel Assisted Chosen-Ciphertext Attacks on NTRU-based KEMs
Ravi P., Ezerman M., Bhasin S., Chattopadhyay A., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2022(1), 722–761